1. Field of the Invention
The present invention relates to a method for fabricating semiconductor devices. More specifically, the present invention relates to a method for fabricating a Metal-Oxide-Semiconductor (MOS) transistor device with a recess channel of a trench type Dynamic Random Access Memory (DRAM).
2. Description of the Prior Art
Integrated circuit devices are continually being made smaller in order to increase speed, make the device more portable and to reduce the cost of manufacturing the device. However, certain designs have a minimum feature size, which cannot be reduced without compromising the integrity of electrical isolation between devices and consistent operation of the device. For example, dynamic random access memory devices (DRAMs), which use vertical metal oxide semiconductor field effect transistors (MOSFETs) with deep trench (DT) storage capacitors, have a minimum feature size of approximately 70 nm˜0.15 μm. Below that size, the internal electric fields exceed the upper limit for storage node leakage, which decreases retention time below an acceptable level. Therefore, there is a need for different methods and/or different structures to further reduce the size of integrated circuit devices.
With the continued reduction in device size, sub-micron scale MOS transistors must overcome many technical challenges. As MOS transistors become narrower (that is, their channel length decreases), problems such as junction leakage, source/drain breakdown voltage, and data retention time become more pronounced.
One solution to decreasing the physical dimension of ULSI circuits is to form recessed-gate or “trench-type” transistors, which have a gate electrode buried in a groove formed in a semiconductor substrate. This type of transistor reduces short channel effects by effectively lengthening the effective channel length by having the gate extend into the semiconductor substrate.
The recessed-gate MOS transistor has a gate insulation layer formed on the sidewalls and bottom surface of a recess etched into a substrate, a conductive filling the recess, contrary to a planar gate type transistor having a gate electrode formed on a planar surface of a substrate.
However, the aforesaid recessed-gate technology has some shortcomings. For example, gate trenches of the conventional hole type recess channel MOS transistor device are formed in the semiconductor substrate by utilizing a lithography process and dry etching process. When utilizing the lithography process to form the hole type gate trenches, the hole contour is not easy to control, and the critical dimension variation cannot be controlled in a range (3 sigma, 15 nm) required in semiconductor processes under 60 nm. Therefore, the short problem between the transistors will occur.